Electronic applications having a digital device with a processor often use an external frequency determining element(s) and/or external oscillator, e.g., crystal or ceramic resonator and/or electronic circuit, to establish a stable time base for determining periodic wake-up from a low power, e.g., standby or sleep, mode. Should this external frequency determining element(s)/oscillator stop for any reason, the processor of the digital device will remain asleep unless awoken to an operational mode by another trigger event. A possible work around to this problem is to enable a watchdog timer in the digital device and use it as a failsafe if failure of the external oscillator should occur. However, use of the watchdog timer in the digital device may excessively raise sleep (standby) current consumption of the digital device and possibly other closely interrelated device applications. Therefore, to lower the power consumption of the digital device the watch-dog timer is typically disabled. Without a wakeup trigger signal from the watch-dog timer to the processor of the digital device, the processor will remain asleep if the external oscillator should fail when the processor is in the low power mode. Alternately (in an operational mode) the processor must remain awake long enough to verify that the external frequency determining element(s)/oscillator is operating. This additional time spent in the operational mode will increase power consumption of the digital device.